Showing posts with label Important Questions. Show all posts
Showing posts with label Important Questions. Show all posts

Saturday, 30 November 2013

CS2302 Computer Networks (CN) - Expected question for NOV/DEC 2013



ANNA UNIVERSITY



INFORMATION TECHNOLOY

(COMMON TO CSE)


EXPECTED QUESTION FOR NOV/DEC 2013


UNIT I

1. OSI Network Architecture.
2. Issues in Data Link Layer (8m)
3. Error correction and error detection.


UNIT II

1. Explain Ethernet.
2. Explain Token Ring and example.
3. Wireless LAN.


UNIT III

1. Disguinguish between Circuit Switching and Pack Switching.
2. ARP and RARP protocol.
3. DHCP.
4. ICMP
5. Congestion avoidance in Network Layer.


UNIT IV

1. UDP
2. TCP
3. Congestion control and Congestion avoidance.


UNIT V

1. DNS
2. Explain E-mail with SMTP, MIME, IMAP and POP3 protocols.
3. HTTP


Thursday, 28 November 2013

MA2265 Discrete Mathematics - Previous Year Question Paper



MA2265 DISCRETE MATHS

COMMON TO CSE

ANNA UNIVERSITY



DOWNLOAD HERE 


MAY/JUNE 2012 PREVIOUS YEAR QUESTION PAPER -> CLICK HERE

NOV/DEC 2010 PREVIOUS YEAR QUESTION PAPER -> CLICK HERE

NOV/DEC 2011 PREVIOUS YEAR QUESTION PAPER -> CLICK HERE

NOV/DEC 2012 PREVIOUS YEAR QUESTION PAPER-> CLICK HERE







Wednesday, 27 November 2013

IT2042 INFORMATION SECURITY - EXPECTED QUESTION FOR NOV/DEC 2013


IT DEPARTMENT
FINAL YEAR


UNIT I

1. NSTISSC Security Model.
2. The SDLC
3. The Security SDLC


UNIT II

1. Write brief notes on Business Needs.
2. Explain Threats.
3. Explain Attacks

UNIT III

1. Risk Management.
2. Identifying risk and accessing risk.


UNIT IV

1.  NIST model.
2. VISA Internet Security Model.
3. Blueprint for Security.

UNIT V

1. Explain IDS.
2. Write about Cryptography in IS.
3. Security and Personnel in IS.



ALL THE BEST :)

IT2042 Information Security Important Questions / Expected Questions for NOV/DEC 2013


IT DEPARTMENT
FINAL YEAR


UNIT I

1. NSTISSC Security Model.
2. The SDLC
3. The Security SDLC


UNIT II

1. Write brief notes on Business Needs.
2. Explain Threats.
3. Explain Attacks

UNIT III

1. Risk Management.
2. Identifying risk and accessing risk.


UNIT IV

1.  NIST model.
2. VISA Internet Security Model.
3. Blueprint for Security.

UNIT V

1. Explain IDS.
2. Write about Cryptography in IS.
3. Security and Personnel in IS.



ALL THE BEST :)

Friday, 22 November 2013

IT2401 Service Oriented Architecture (SOA) - Important / Expected Question for NOV/DEC 2013



IT 2401 SOA
(INFORMATION TECHNOLOGY)

EXPECTED QUESTIONS FOR NOV/DEC 2013


UNIT I

1. Characteristics of SOA.
2. Comparing SOA to Client-Server and Distributed Architecture.
3. Principles of Service Orientation.


UNIT II

1.  Messaging with SOAP.
2.  Message Exchange Pattern.
3. Atomic Transaction.
4. Service Layer Abstraction.


UNIT III

1. Service Oriented Analysis.
2. Service Oriented Modelling.
3. Service Oriented Designing.
4. WSDL Basic & SOAP Basic.


UNIT IV

1. WS support in J2EE.
2. WS support in .NET


UNIT V

1. WS-Policy.
2. WS-Security.
3. WS BPEL Basics.



All the best :)



Thursday, 21 November 2013

CS2304 SYSTEM SOFTWARE IMPORTANT QUESTIONS FOR FIFTH SEMESTER IT & CSE



Unit-1:
1)Explain SIC machine architecture in detail.
2)Explain SIC/XE machine architecture in detail.
3)Comparison of CISC and RISC

Unit-2:
1)Explain One pass assembler with algorithm.
2)Explain Two pass assembler with algorithm.
3)Explain multipass assembler.
4)Explain Machine Dependent assembler features in detail.
5)Explain Machine In-dependent assembler features in detail.

Unit-3:
1)Explain MS-Dos Linker.
2)Explain Various steps involved in Absolute loader ans Bootstrap loader.
3)Explain Design options of Loader
4)Explain Relocating Loaders.
5)Dynamic Linking(Load on call)

Unit-4
1)MASM Macro Processor
2)Macro vs Subroutine
3)Algorithm and data structures for a Macro Processor
4)One Pass Macroprocessor
5)Macro processor Design options

Unit-5
1)Interactive debugging system
2)Text editor
3)User interface and their importance
4)Editor structure

Thursday, 2 May 2013

NOTES FOR THE 6th SEMESTER .......... INFORMATION TECHNOLOGY DEPT

NOTES FOR THE 6th SEMESTER .......... INFORMATION TECHNOLOGY DEPT

pls click the link below to download the notes.........

https://docs.google.com/file/d/0B1MEIl-F-DIQbncyM3VmekplTDA/edit?usp=sharing

BITSA wishes all its subscribers all success for the exams!!!!!!!!

further notes to be updated soon.........

Friday, 29 March 2013

IT2354 Embedded System - Important Question Bank (2 marks and 16 marks)



Anna University
Department of Information Technology
Sub. Code & Name: IT 2354 Embedded Systems
Class: 3 IT Question Bank

Embedded Systems  Question Bank – 2012 Edition
(All Units)

Unit-I
Embedded Computing
Part-A (2 Marks)

1. Define embedded system. What are the three main components of an embedded system?
2. What are the components of Embedded System hardware?
3. Why micro processor is used in embedded system?
4. What is the purpose of the z bit?
5. List the characteristics of embedded system.
6. Define a System.
7. What are the various classifications of embedded systems?
8. Give the hardware model of an embedded system.
9. What are the constraints to be considered while designing an embedded system?
10. List the characteristics of an embedded system.
11. Give some examples for sophisticated embedded systems.
12. Compare little and big-endian modes in ARM processor.
13. List the various instructions used in ARM with one example each.
14. Implement the statement x= (a+b)-c, using ARM instructions.
15. Differentiate embedded processor and embedded microcontroller.
16. Differentiate IO bit and IO byte programming.
17. What do you meant by load store concept?
18. List the various bits in CPSR.
19. Write an 8051 C program to send values 00-FF to port P1.
20. Write an 8051 C program to toggle bit D0 of the port P1 (P1.0) 50,000 times.
21. Show the status of the CY, AC, and P flags after the addition of 9CH and 64H in the following instructions.
MOV A, #9CH ADD A, #64H
22. Differentiate top-down and bottom-up designs
23. Write an 8051 C program to monitor bit P1.5. If it is high, send 55H to P0; otherwise, send AAH to P2.
Part-B (16 Marks)
1. Explain in detail the design process in embedded system. [16]
2. What are the challenges of Embedded System? [8]
3. Explain various architectural features of 8051 micro processor. [8]
4. Explain ARM Processor, Architecture, Instruction set Programming. [16]
5. Discuss the data operations of ARM processor. [8]
6. (i) What are the various problems that must be taken into account in embedded system design? [8]
(ii) List the hardware units that must be present in the embedded systems. [8]
7. (i) Explain the various data operations involved in ARM. [8]
(ii) Implement an if statement in ARM. [8]
8. With the help of a neat block diagram explain the 8051 processor. [16]
9. (i) List the various types of instructions in 8051. [8] (ii) Write an 8051 C program to toggle all the bits of P0, P1, and P2 continuously with a 250 ms delay. Use the sfr keyword to declare the port address. [8]

Unit-II
Memory and Input/Output Management
Part-A (2 Marks)

1. Why do most computer systems use memory-mapped I/O?
2. Give the structure of a basic IO device.
3. Define Aspect ratio of the memory.
4. List the features of RAM bus.
5. Define polling.
6. What do you meant by a foreground program?
7. What are maskable and non-maskable interrupts?
8. What are the interrupts that are being supported by ARM?
9. Define cache hit and cache miss.
10. Define working set.
11. Compare write through and write back.
12. Give the types of cache miss.
13. What do you meant by set associative cache?
14. Define memory mapping and virtual addressing.
15. Define boot-block flash.
16. Compare RAM and ROM.
17. Differentiate timers and counters.
18. What is the use of a watchdog timer?
19. List the various IO devices.
20. What is interfacing? Give its types.

Part-B (16 Marks)
1. (i) Along with the structure of a cache memory explain it. [8]
(ii) Explain the memory management units and address translation techniques. [8]
2. Explain in detail the programming of input and output devices. [16]
3. (i) List the various input and output devices and explain them in detail. [8]
(ii) Explain the various memory devices along with component interfacing. [8]
4. Explain the various interrupt handling mechanisms. [16]
5. Discuss the memory devices and its interfacing concepts. [8]
6. Discuss the I/O devices & its interfacing concepts? [8]

Wednesday, 26 December 2012

CS2411 Operating Systems Important Questions Nov/Dec 2012 - Anna University,Chennai



Operating Systems CS2411 Nov/Dec 2012 Important Questions - Anna University,Chennai


Anna University, Chennai Nov/Dec 2012 Examinations
Important Questions
Operating Systems CS2411
7th Sem EEE
Unit I-V
1.     Explain in detail about Operating System Structures.
2.     Explain the Types of System Calls in detail.
3.     Explain about inter process communication.
4.     Explain in detail about virtual machines.
5.     What is meant by a process? Explain states of process with neat sketch and discuss the process state transition with a neat diagram
6.     Explain briefly any four CPU scheduling algorithms with examples.(Problem + Theory)
7.      Explain Banker’s deadlock-avoidance algorithm with an illustration.
8.     Give a detailed description about deadlocks and its  characterization.
9.     Explain what semaphores are, their usage, implementation given to avoid busy waiting and binary semaphores.
10.Explain about the techniques for structuring the page table.
11. Explain the various page replacement strategies.(With example)
12.Discuss about Swapping b) Paging c) Segmentation d) TLB hit/miss
13.Explain various file allocation methods and free space management with neat diagram.
14. What are the directory implementation techniques available? Explain in detail.
15.Explain the various directory structure in detail.
16. Explain the various disk scheduling techniques
17.What is meant by RAID levels? Which level is used for what purpose?
18.Write in detail about the kernel I/O subsystem and I/O hardware.19.Write notes about disk management.

Tuesday, 25 December 2012

EE350 Computer Architecture - April/May 2012 - VI Semester - EEE Important question

B.E./B.Tech. DEGREE EXAMINATION,APRIL/MAY 2010
VI - SEMESTER
B.E. ELECTRICAL AND ELECTRONICS ENGINEERING
EE350 - COMPUTER ARCHITECTURE

Time: 3hrs Max Marks: 100
Answer all Questions
PART – A (10 x 2 = 20 Marks)

1. What is MAR and MBR? What will be the content of MAR and MBR for read and write operation?

2. Define stack. Following operations were performed on stack, which contains an integer item 10.
Push 20, Push 30, Pop, Push 40, Pop, Pop.
What will be the top element of stack after above all operations were completed?

3. Explain with an example, the 2's compliment subtraction.

4. Define Bit-slice processing. What is a bit slice?

5. RISC processors typically have instructions of equal size. What is advantage of such choice?

6. Define micro instruction and micro program.

7. What is the need for memory hierarchy?

8. Define hit ratio. Give the relation between hit ratio and access efficiency.

9. What is an interrupt? Mention its need.

10. Draw block diagram of DMA controller.

PART – B (5 x 16 = 80 Marks)

11. (i) Discuss about the various instruction formats. (8)
(ii) Explain stack organization. (8)

12.a) Draw and explain the flow chart of floating point arithmetic operation for addition and subtraction. (16)

OR

b) Explain Booth algorithm for multiplying two binary numbers. (16)

13.a) Explain about micro programmed control unit with a neat diagram. (16)

OR

b) Design a computer with 512 bytes of RAM 1024 bytes of ROM. The memory is available in 128 bytes RAM chips and 512 bytes of ROM chips. Select appropriate size address and data buses. If needed decoders can be used. Draw the connection and show the address mapping. (16)

14.a)i) Define virtual memory. What is the necessity for using the concept of virtual memory? (16)

ii) Explain with a neat diagram how address mapping is done in paging system. (16)

OR

b) Define Cache memory. Explain anyone mapping procedure. (16)

15.a) Explain programmed IO system and IO processor. (16)

OR

b) (i) Discuss an IO processor and its organization. (12)
(ii) Explain how priority in interrupts are handled. (4)
 

Tuesday, 11 December 2012

CS2202 Digital Principles and Systems Design Important questions for nov/dec 2012 exams - anna university,chennai


Anna University,Chennai Nov/Dec 2012 Examinations
  Important Questions
Digital Principles and Systems Design CS2202
UNIT I-V
 
 
1.     Reduce the expression using Quine McCluskey method F(x1,x2,x3,x4,x5)=∑m(0, 2,4,5,6,7,8,10,14,17,18,21,29,31) + ∑d (11, 20, 22)
2.     Explain the conversion of regular expression into canonical expression and their simplification in SOP and POS forms
3.     Determine the minterm sum of product form of the switching function F = ∑ (0, 1, 4, 5, 6, 11, 14, 15, 16, 17, 20,21,22, 30, 32, 33, 36, 37, 48, 49, 52,53, 59, 63)
4.     Using Tabulation method simplify the Boolean function F(w, x, y, z) =  ∑ (1, 2, 3, 5, 9, 12, 14, 15) which has the don’t care condition d(4, 8, 11)
5.     With a suitable block diagram explain the operation of BCD adder
6.     Draw and explain the working of a carry-look ahead adder
7.      A circuit receives only valid 5211 or 8421 BCD information and provides two output lines X and Y Design the circuit such that X will provide an output anytime a valid 8421 BCD code appears at the input and Y will provide an output anytime a valid 5211 BCD code appears at the input
8.     Design Full adder and subtractor circuits using NAND and NOR gates respectively
9.     Implement the switching function z1=ab’d’e+a’b’c’d’e’+bc+de, z2==a’c’e, z3=bc+de+c’d’e’+bd, z4==a’c’e+ce using 5X8X4 programmable logic array
10.Explain with necessary diagram a BCD to 7 segment display decoder
11. Design a 3 to 8-line decoder with necessary diagram
12.Implement a full adder with two 4*1 multiplexers
13. Write the HDL for the above circuit
14.Design MOD 6 synchronous sequential circuit using JK flipflip
15. Design and explain the working of a up-down ripple counter
16.Design a synchronous sequential circuit using JK flip-flop to generate the following sequence and repeat.  0, 1, 2, 4, 5,
17. With suitable example and diagram explain the hazards in combinational and sequential logic circuits
18.Design  the Tflip flop from the logic gates  
19.Design a non sequential ripple counter which will go through the states        3,4,5,7,8,9,10,3,4………………..draw bush diagram
20.                   Find a circuit that has no static hazards and implements the Boolean function F(A,B,C,D)=∑  m(1,3,5,7,8,9,14,15)
21.Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one    output Z. When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0.

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