The
SIC Machine
_ SIC
Simplified Instructional Computer
_ simplest
version
_ Instructional
: programmable
_ SIC/XE
: SIC XE version
_ XE :
extra equipment
_ XE :
extra expensive
_ Hypothetic
machine
_ simple,
concise
_ almost
including everything used in modern computers
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Learning
a CPU
Form a
programming point of view to learn a CPU
_ Architecture
_ Memory
_ Registers
_ Data
Formats
_ Instructional
Formats
_ Addressing
Modes
_ Instruction
Set
_ Input
/ Output
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Architecture
CPU
. . .
0 1 2 3 . . .
HDD
TFT LCD
KeyBoard
Mouse
CD-ROM
. . .
Peripherals
Memory
bus
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SIC
Memory
_ bit,
byte, word
_ byte
= 8 bits
_ 1
word = 3 bytes = 24 bits
_ total
memory size 215 = 32768 Bytes = 32K Bytes
_ magic
number 15
0 1 2 7FFE 7FFF
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SIC
: Registers
_ A 0
Accumulator
arithmetical operation
default operand
_ X 1
IndeX
for indexed addressing
_ L 2
Linkage
non-stack equipped machine
used for return address of
function call
_ PC 8
program counter
_ SW 9
Status Word (System Flags)
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SIC
: Data Formats
_ integers
_ 24-bit
_ unsigned : 0 .. 16,777,215 (=16M-1)
_ signed : -8,388,608 .. 8,388,607
_ 2’s
complement
_ characters
_ 8-bit
_ ASCII
code
_ floating
point
_ not
implemented in SIC
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SIC
: Instruction Formats
_ machine
code instruction formats
_ recall
a instruction is to perform an operation
_ operator
:
_ assembly language :
mnemonic
_ machine code : opcode
_ operands
_ single
format
_ opcode
: op-tab instruction table
_ addr
: memory address of the operand of the instruction
X
1
addr
15
opcode
8
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SIC
: Addressing Mode
_ single
operand instruction :
_ register
/ memory / immediate (constant)
_ addressing
mode :
_ representation
of memory addressing in machine code
form
_ addr
: third field of instructions in SIC machine code
_ target
address (TA) : memory location address
_ x-bit
of instructions in the SIC machine code
_ direct addressing TA =
addr x = 0
_ indexed addressing TA =
addr + (X) x = 1
_ (X) content of register X
(dereferencing operator)
X
1
addr
15
opcode
8
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SIC
: Instruction Set
_ load
/ store registers
_LDA /
STA / LDX / STX
_ arithmetic
operations
_ADD /
SUB / MUL / DIV
_ logical
opertions
_COMP
_ conditional
jump
_JMP /
JGT / JLT / JEQ
_ subroutine
linkage
_JSUB
(call) RSUB (return)
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ADD m 18 0001
1000 A := (A) + (m..m+2)
SUB m 1C 0001
1100 A := (A) − (m..m+2)
MUL m 20 0010
0000 A := (A) * (m..m+2)
DIV m 24 0010
0100 A := (A) / (m..m+2)
AND m 40 0100
0000 A := A & (m..m+2)
OR m 44 0100
0100 A := A | (m..m+2)
J m 3C 0011
1100 PC := m
JEQ m 30 0011
0000 PC := m if CC is =
JGT m 34 0011
0100 PC := m if CC is >
JLT m 38 0011
1000 PC := m if CC is <
RSUB 4C 0100
1100 PC := (L)
JSUB m 48 0100
1000 L:=(PC); PC:=m
SIC
: Instruction Set (1)
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LDA m 0C 0001
1000 A := (m..m+2)
LDCH m 50 1001
0000 A[l.s.b] := (m..m+2)
LDX m 94 1001
0100 X:= (m..m+2)
STA m 0C 0001
1000 (m..m+2) := A
STB m 68 0101
1000 (m..m+2) := B
STCH m 50 1001
0000 (m..m+2) := A[l.s.b]
STX m 94 1001
0100 (m..m+2) := X
COMP m 2B 0010
1101 A : (m..m+2)
TIX m 2C 0010
1100 X:=X+1; (X):(m..m+2)
TD m E0 1100
0000 A := (A) − (m..m+2)
RD m D8 1101
1000 F := (F) − (m..m+5)
WD m DC 1101
1100 r2 := r1 − r2
SIC
: Instruction Set (2)
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SIC
: Input / Output
_ transferring
1 byte at a time to/from device
_ TD :
test device
_ if it
is ready for action (read or write)
_ repeat
testing until the device is available (not busy)
_ WD :
write data (a byte) to device
_ RD :
read data (a byte) from device
